The present invention relates to a D-RAM (dynamic random-access memory) integrated circuit device comprising MISFETs (metal insulator semiconductor field-effect transistors).
In a typical D-RAM, a memory array comprises a plurality of memory cells arranged in a matrix, data lines and word lines. In reading out data, a minute potential change is applied to a data line from a memory cell which is formed of a single transistor. In order to permit amplification of such a minute potential change, two data lines are paired in ordinary D-RAMs. When the stored data in the memory cell connected to one data line of such a data line pair is read out, a reference potential is applied to the other data line of the data line pair by a proper means such as a dummy cell. The potential difference between the lines constituting the data line pair is amplified by means of a sense amplifier.
In reading out data from the memory cells, a potential fluctuation which is considered to be noise is applied to each of the data lines from a word line through an undesirable capacitance such as a parasitic capacitor. It has been found in the past that the effect due to this potential fluctuation can be significantly reduced by means of a folded bit line arrangement. In other words, a single word line is made to smultaneously apply a noise which is considered to be a common mode noise to both the lines constituting the data line pair. The common mode noise can be substantially neglected by means of a differential type sense amplifier. Consequently, it becomes possible to read out data from the memory cells with substantially no error independently of the undesirable potential fluctuation applied to the data lines from the word line.
The inventor, however, has discovered through his further studies that a relatively large differential mode noise is applied to the data line pair located at an end part of the memory array even when such a folded bit line arrangement is used. This differential mode noise is produced due to the word line selecting operation and the substrate bias voltage fluctuation. Accordingly, although the folded bit line arrangement offers significant advantages, it still can have unresolved noise problems.